{
  "source": "Cooked Index — occupational AI risk register",
  "page": "https://cookedindex.com/jobs/computer-hardware-engineers/",
  "methodology": "https://cookedindex.com/methodology",
  "notice": "Verdicts are re-examined as evidence accumulates. Re-fetch before relying on this; the page above always carries the current score.",
  "scored_at": "2026-08-11",
  "model": "claude-opus-5",
  "occupation": {
    "title": "Computer Hardware Engineers",
    "soc_code": "17-2061",
    "category": "Engineering",
    "us_employment": 76660,
    "median_annual_wage": 161740
  },
  "verdict": "EXPOSED",
  "risk_resistance": 40,
  "contested": false,
  "near_boundary": false,
  "dimensions": {
    "task_resistance": 10,
    "embodiment": 10,
    "liability_shield": 3,
    "trust_premium": 5,
    "judgment_accountability": 12
  },
  "reasoning": {
    "task_resistance": "RTL coding, testbench generation, constraint files, Tcl/Python flow scripts and datasheet-driven spec documents are all text artifacts that LLM tooling already drafts to a reviewable standard, which is why this sits at 10 rather than 15 — but post-silicon bring-up, root-causing a marginal DDR eye or an intermittent brownout on a real board, still cannot be done from a prompt.",
    "embodiment": "A 10 reflects the split week: most hours in Vivado/Quartus, Cadence or Synopsys on a workstation, then real time in the lab with a 4-GHz scope, TDR, thermal camera and an anechoic or GTEM chamber, soldering rework and reflashing boards — physical, but in a climate-controlled lab bench, not a rooftop or a trench, which keeps it well below the 13+ field-work band.",
    "liability_shield": "The industrial exemption means almost no hardware engineer stamps anything as a PE; sign-off on a tapeout or an ECO is an internal gate approved by a design-review board and a program manager, and IPC or UL certification attaches to the product and the test house, not to your name — the 3 is for that near-total absence of a personal licence.",
    "trust_premium": "Your output is a netlist, a Gerber stack-up and a bring-up report that a fab, an OSAT or a contract manufacturer consumes without knowing who authored it; the 5 rather than 0 covers the standing you build with a specific foundry PDK team, package vendor or SoC integration lead who takes your word on a corner-case waiver.",
    "judgment_accountability": "Committing a mask set at $2-10M, waiving a timing violation on a hold path, or declaring a board fit for volume manufacture are ambiguous calls made on incomplete silicon data with schedule pressure — genuine discretion, but bounded by DRC/DFM rules, signoff corners, qual standards like JEDEC and AEC-Q100, and a review chain above you, which places it at 12 not 17."
  },
  "rationale": "Most of the day is screen work inside EDA tools — writing RTL and testbenches, running synthesis and timing closure, scripting flows in Python/Tcl, drafting specs — and AI already produces usable first drafts of all of it. What holds is the physical half: silicon bring-up on the bench, scope-and-probe debug of signal integrity and power delivery, thermal and EMC validation, and the accountable call to commit a multi-million-dollar mask set or release a board to manufacturing. No PE license gates the work in practice, so there is no regulatory floor under the job.",
  "outlook": "Headcount per design team shrinks as AI absorbs RTL, scripting, and documentation, while demand concentrates on engineers who can debug real hardware and own tape-out and release decisions.",
  "what_would_raise_it": {
    "levers": [
      {
        "dimension": "task_resistance",
        "change": "Task-mix shift: RTL drafting, testbench generation, Tcl/Python flow scripting and spec boilerplate are the routine tier and are already being absorbed by EDA-vendor LLM assistants (Synopsys.ai Copilot, Cadence Cerebrus/JedAI, Siemens). What remains is the judgment tier — architectural partitioning and power/perf/area tradeoffs, post-silicon failure triage where the bug is not in the RTL, and correlating bench anomalies to a design defect. If routine hours drop out, the residual day is dominated by work AI cannot close, and this rises without any legal change.",
        "plausibility": "already happening",
        "would_add": 4
      },
      {
        "dimension": "embodiment",
        "change": "Post-silicon bring-up, scope-and-probe SI/PDN debug, thermal chamber and EMC pre-compliance work grows as a share of the role, and shifts further toward chiplet/advanced-packaging bring-up where failures are mechanical and thermal rather than logical. If US fab and OSAT capacity additions under the CHIPS Act put more first-silicon bring-up benches domestically, hands-on hours per engineer rise.",
        "plausibility": "plausible",
        "would_add": 3
      },
      {
        "dimension": "liability_shield",
        "change": "Two concrete routes: (a) safety-standard sign-off — ISO 26262 ASIL-D and DO-254 already require a named responsible engineer for hardware design assurance; if certification bodies or automotive/avionics OEM contracts add an explicit clause that AI-generated RTL or synthesis output requires attestation by an identified human design authority, a review-and-sign gate becomes contractual. (b) Export/security attestation — CHIPS Act security requirements and DoD trusted-supplier rules (DMEA Trusted Foundry, DFARS) attaching a named engineer's certification to hardware provenance and absence of undocumented functionality. Neither is a PE license, but both create personal named accountability.",
        "plausibility": "plausible",
        "would_add": 4
      },
      {
        "dimension": "judgment_accountability",
        "change": "Mask-set tapeout commitment already carries seven-to-eight-figure consequences under genuine ambiguity. This tightens if firms formalize the tapeout readiness review with a named signing owner — some already do this for automotive and datacenter silicon — or if an insurer underwriting recall/warranty exposure requires an identified accountable engineer for release-to-manufacturing.",
        "plausibility": "plausible",
        "would_add": 3
      }
    ],
    "ceiling_note": "Trust premium has no realistic route: buyers of chips and boards purchase parts and specs, and never see or select the engineer, so there is no channel to pay extra for a human. Liability shield is also capped — no US state gates hardware design behind a PE stamp in practice, and the electrical PE exemption for industry employees is entrenched, so gains here come from private contracts and standards rather than licensure and could be renegotiated away."
  },
  "adjudication": null,
  "employment_history": {
    "points": [
      {
        "y": 2017,
        "emp": 66770,
        "wage": 115120
      },
      {
        "y": 2018,
        "emp": 60750,
        "wage": 114600
      },
      {
        "y": 2019,
        "emp": 67880,
        "wage": 117220
      },
      {
        "y": 2020,
        "emp": 64710,
        "wage": 119560
      },
      {
        "y": 2021,
        "emp": 73750,
        "wage": 128170
      },
      {
        "y": 2022,
        "emp": 74640,
        "wage": 132360
      },
      {
        "y": 2023,
        "emp": 82660,
        "wage": 138080
      },
      {
        "y": 2024,
        "emp": 75710,
        "wage": 155020
      },
      {
        "y": 2025,
        "emp": 76660,
        "wage": 161740
      }
    ],
    "from": 2017,
    "to": 2025,
    "change_pct": 14.8,
    "comparable_from": 2019,
    "spans_soc_revision": true
  },
  "pivots": [],
  "license": "https://cookedindex.com/terms"
}