EXPOSED
Most of the day is screen work inside EDA tools — writing RTL and testbenches, running synthesis and timing closure, scripting flows in Python/Tcl, drafting specs — and AI already produces usable first drafts of all of it. What holds is the physical half: silicon bring-up on the bench, scope-and-probe debug of signal integrity and power delivery, thermal and EMC validation, and the accountable call to commit a multi-million-dollar mask set or release a board to manufacturing. No PE license gates the work in practice, so there is no regulatory floor under the job.
Dipped in 2020, then grew past where it started.
Median pay $117,220 → $161,740 +10.4% in real terms
This line is counted by the Bureau of Labor Statistics — the one figure on this page that isn't a judgement of ours. Headcount moves on demand, offshoring, demographics and the business cycle, and automation is one term among several, often not the loudest.
So a falling line is not evidence that AI did it, and a rising one is not evidence that it won't. Both happen in this register: some occupations resist automation and shrink anyway, others are highly automatable and keep growing. The marked year is 2020.
BLS projection, 2024–2034
+7.3% 76,800 → 82,400 on the projections basis
Exposed, but growing
AI can already do a lot of these tasks, and the BLS still expects +7.3% more of these jobs by 2034. Demand for the output is growing faster than the work is being automated away — the mechanism BLS gives for software developers, and the combination people most often misread as an error.
Different clocks. The score is what current AI could do to this work today. The projection is how many of these jobs will exist in 2034. Everything between the two — how fast employers actually adopt, whether demand grows in the meantime — is why they can point opposite ways without either being wrong.
~4,700 openings a year on average, including replacing people who leave.
EngineerStaff EngineerComputer TesterDesign EngineerProject EngineerComputer DesignerComputer EngineerHardware EngineerHardware ArchitectElectronics EngineerMicrochip SpecialistAnalog Design EngineerField Service EngineerHardware Test EngineerDigital Design EngineerComputer Vision EngineerHardware Design EngineerPhysical Design EngineerDigital Hardware EngineerHardware Systems EngineerSignal Integrity EngineerComputer Hardware DesignerComputer Hardware EngineerEmbedded Hardware Engineer
Holding it up: judgment & accountability . Weakest point: liability shield .
Mixed — a routine tier and a judgment tier RTL coding, testbench generation, constraint files, Tcl/Python flow scripts and datasheet-driven spec documents are all text artifacts that LLM tooling already drafts to a reviewable standard, which is why this sits at 10 rather than 15 — but post-silicon bring-up, root-causing a marginal DDR eye or an intermittent brownout on a real board, still cannot be done from a prompt.
Some physical or field component A 10 reflects the split week: most hours in Vivado/Quartus, Cadence or Synopsys on a workstation, then real time in the lab with a 4-GHz scope, TDR, thermal camera and an anechoic or GTEM chamber, soldering rework and reflashing boards — physical, but in a climate-controlled lab bench, not a rooftop or a trench, which keeps it well below the 13+ field-work band.
No licence, no signature requirement The industrial exemption means almost no hardware engineer stamps anything as a PE; sign-off on a tapeout or an ECO is an internal gate approved by a design-review board and a program manager, and IPC or UL certification attaches to the product and the test house, not to your name — the 3 is for that near-total absence of a personal licence.
Meaningful discretion Committing a mask set at $2-10M, waiving a timing violation on a hold path, or declaring a board fit for volume manufacture are ambiguous calls made on incomplete silicon data with schedule pressure — genuine discretion, but bounded by DRC/DFM rules, signoff corners, qual standards like JEDEC and AEC-Q100, and a review chain above you, which places it at 12 not 17.
The verdict above describes this occupation as a whole. Almost nobody does the typical version of a job — tick what's actually in your week and see how your own mix sits.
Your task mix speaks to task resistance (10/20 here) — how much of the day's work current AI already does. That is the dimension the boxes above are about.
It cannot move the other three. Liability shield (3/20) is whether the law requires a licensed human to sign. Trust premium (5/20) is whether buyers specifically pay for a person. Judgment and accountability (12/20) is whether the role exists to own consequential calls. Those are facts about the occupation's standing, not about which tasks are in your week — a paralegal who does only trial exhibits still holds no licence. Together they are 20 of this occupation's 40 points (50%).
Embodiment (10/20) is also a property of the work rather than the worker, but we don't tag individual tasks as physical or not, so the picker can't tell you anything about it. That's a limit of this tool, not a claim.
Did we get the list right? Tell us what's missing — the tasks are written from the outside, and you're reading this from the inside.
No occupation passed every test: close enough to computer hardware engineers on skills and subject matter, at least 10 points more resistant, no big jump in training, no new licence, no pay cut, and not shrinking on its own. That happens for 223 of the 654 occupations here that aren't SAFE, and it is worth stating plainly rather than leaving the section off.
The usual reason is that exposure travels with the skill profile. The jobs most similar to yours tend to be exposed for the same reasons yours is, so the near neighbours don't clear the gap — and the ones that do are a different kind of work, not a transfer of what you already know. Read that as a limit of this method, not a verdict that you're stuck: it only compares whole occupations, and it cannot see specialisation, industry, or anything you'd bring that isn't in a federal skill survey.
Here is that claim on your own job rather than in the abstract. These are the three occupations closest to this one by skill and subject matter — the places the work would most naturally transfer — with what the register scores them:
That is the whole problem in three lines. The nearest work is not meaningfully safer, so there is no move here that trades a similar skill set for a better verdict. This is not us running out of ideas — it is what the neighbourhood looks like.
The moves above are yours to make. This is the other half: what would have to change in the world for the occupation itself to score higher. None of it is in any one person's gift, but it is where the floor actually comes from. Scores here are not a one-way ratchet. Only two of the five dimensions — task resistance and embodiment — track what machines can do. The other three track law, what buyers will pay for, and who is answerable, and those move in both directions, often in response to the same pressure AI creates. If every lever below landed, this occupation would score around 54/100, still EXPOSED.
Task-mix shift: RTL drafting, testbench generation, Tcl/Python flow scripting and spec boilerplate are the routine tier and are already being absorbed by EDA-vendor LLM assistants (Synopsys.ai Copilot, Cadence Cerebrus/JedAI, Siemens). What remains is the judgment tier — architectural partitioning and power/perf/area tradeoffs, post-silicon failure triage where the bug is not in the RTL, and correlating bench anomalies to a design defect. If routine hours drop out, the residual day is dominated by work AI cannot close, and this rises without any legal change.
Two concrete routes: (a) safety-standard sign-off — ISO 26262 ASIL-D and DO-254 already require a named responsible engineer for hardware design assurance; if certification bodies or automotive/avionics OEM contracts add an explicit clause that AI-generated RTL or synthesis output requires attestation by an identified human design authority, a review-and-sign gate becomes contractual. (b) Export/security attestation — CHIPS Act security requirements and DoD trusted-supplier rules (DMEA Trusted Foundry, DFARS) attaching a named engineer's certification to hardware provenance and absence of undocumented functionality. Neither is a PE license, but both create personal named accountability.
Post-silicon bring-up, scope-and-probe SI/PDN debug, thermal chamber and EMC pre-compliance work grows as a share of the role, and shifts further toward chiplet/advanced-packaging bring-up where failures are mechanical and thermal rather than logical. If US fab and OSAT capacity additions under the CHIPS Act put more first-silicon bring-up benches domestically, hands-on hours per engineer rise.
Mask-set tapeout commitment already carries seven-to-eight-figure consequences under genuine ambiguity. This tightens if firms formalize the tapeout readiness review with a named signing owner — some already do this for automotive and datacenter silicon — or if an insurer underwriting recall/warranty exposure requires an identified accountable engineer for release-to-manufacturing.
The limit. Trust premium has no realistic route: buyers of chips and boards purchase parts and specs, and never see or select the engineer, so there is no channel to pay extra for a human. Liability shield is also capped — no US state gates hardware design behind a PE stamp in practice, and the electrical PE exemption for industry employees is entrenched, so gains here come from private contracts and standards rather than licensure and could be renegotiated away.
| San Jose-Sunnyvale-Santa Clara, CA | 7,940 | $209,860 +30% |
| Austin-Round Rock-San Marcos, TX | 3,850 | $165,530 +2% |
| San Diego-Chula Vista-Carlsbad, CA | 3,330 | $174,440 +8% |
| Boston-Cambridge-Newton, MA-NH | 2,840 | $167,600 +4% |
| Phoenix-Mesa-Chandler, AZ | 2,820 | $167,010 +3% |
| San Francisco-Oakland-Fremont, CA | 2,810 | $203,890 +26% |
| Los Angeles-Long Beach-Anaheim, CA | 1,870 | $158,530 -2% |
| Washington-Arlington-Alexandria, DC-VA-MD-WV | 1,790 | $159,480 -1% |
| San Jose-Sunnyvale-Santa Clara, CA | 7,940 | $209,860 +30% |
| San Francisco-Oakland-Fremont, CA | 2,810 | $203,890 +26% |
| Bridgeport-Stamford-Danbury, CT | 120 | $202,390 +25% |
We have no reported case of a named organisation automating this occupation. Not one deployment, not one announcement.
That is worth saying out loud next to a score of 40. The verdict above is about what the work exposes — what current AI could do to these tasks. It is not a claim that anyone has done it. For this occupation those two things have come apart completely: the capability argument is on this page, and the evidence column is empty.
Has AI actually changed your work? One tap, anonymous, and the running tally is public. Nothing else is asked of you.
Rather than check back: get the digest and we'll tell you what changed — or watch a single occupation from its own page.