Computer Hardware Engineers

Mixed — a routine tier and a judgment tier. RTL coding, testbench generation, constraint files, Tcl/Python flow scripts and datasheet-driven spec documents are all text artifacts that LLM tooling already drafts to a reviewable standard, which is why this sits at 10 rather than 15 — but post-silicon bring-up, root-causing a marginal DDR eye or an intermittent brownout on a real board, still cannot be done from a prompt.

Some physical or field component. A 10 reflects the split week: most hours in Vivado/Quartus, Cadence or Synopsys on a workstation, then real time in the lab with a 4-GHz scope, TDR, thermal camera and an anechoic or GTEM chamber, soldering rework and reflashing boards — physical, but in a climate-controlled lab bench, not a rooftop or a trench, which keeps it well below the 13+ field-work band.

No licence, no signature requirement. The industrial exemption means almost no hardware engineer stamps anything as a PE; sign-off on a tapeout or an ECO is an internal gate approved by a design-review board and a program manager, and IPC or UL certification attaches to the product and the test house, not to your name — the 3 is for that near-total absence of a personal licence.

Anonymous artifact production. Your output is a netlist, a Gerber stack-up and a bring-up report that a fab, an OSAT or a contract manufacturer consumes without knowing who authored it; the 5 rather than 0 covers the standing you build with a specific foundry PDK team, package vendor or SoC integration lead who takes your word on a corner-case waiver.

Meaningful discretion. Committing a mask set at $2-10M, waiving a timing violation on a hold path, or declaring a board fit for volume manufacture are ambiguous calls made on incomplete silicon data with schedule pressure — genuine discretion, but bounded by DRC/DFM rules, signoff corners, qual standards like JEDEC and AEC-Q100, and a review chain above you, which places it at 12 not 17.